Download Advanced Parallel Processing Technologies: 9th International by Kunal Korgaonkar, Prabhat Jain, Deepak Tomar (auth.), PDF

By Kunal Korgaonkar, Prabhat Jain, Deepak Tomar (auth.), Olivier Temam, Pen-Chung Yew, Binyu Zang (eds.)

ISBN-10: 3642241506

ISBN-13: 9783642241505

ISBN-10: 3642241514

ISBN-13: 9783642241512

This publication constitutes the refereed court cases of the ninth foreign Symposium on complicated Parallel Processing applied sciences, APPT 2011, held in Shanghai, China, in September 2011.

The thirteen revised complete papers offered have been rigorously reviewed and chosen from forty submissions.
The papers are geared up in topical sections on parallel dispensed approach architectures, structure, parallel program and software program, allotted and cloud computing.

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Extra info for Advanced Parallel Processing Technologies: 9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011. Proceedings

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Hybrid cache architecture with disparate memory technologies. In: ISCA 2009, pp. 34–45 (2009) 9. : Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology. In: IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 98–99 (2008) 10. : Scalable high performance main memory system using phasechange memory technology. In: ISCA-36 (2009) 11. pdf 12. : Power7: IBM’s Next-Generation Server Processor. IEEE Micro. 30(2), 7–15 (2010) 13. Virtutech AB. com/ 14. edu/gems/ 15.

DRAM requires a consistent refresh operation to sustain data and consumes a significant amount of power. Unlike DRAM, PCM is a type of non-volatile memory that can retain its data even when the power is turned off. The PCM cell consists of a standard NMOS access transistor and phase change material, GST (Ge2 Sb2 Te5 ), as shown in Fig. 1. The phase change material is between a top and a bottom electrode with a heating element. When current is injected into the heating element, the phase change is induced.

Only write back request actually produces dirty data lines, and the data lines will be replaced to the next level PCM in future. Therefore, we just distinguish read operations (load/store) from write operations (write back) in our policy. In addition, for organization with DRAM buffer shown in 36 X. Zhang et al. Fig. 2(b), RWA can be used both in on-chip last level cache and DRAM buffer. Moreover, RWA is adaptive for both inclusive and non-inclusive memory. 2 Read-Write Aware Replacement Policy To reduce the write traffic to PCM, we propose RWA policy for memory level above PCM.

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